1. Field of the Invention
The present invention relates to the field of use of digital imaging. More particularly, the present invention relates to analog-to-digital signal processing.
2. Description of Related Art
Digital cameras are becoming an important component of every personal computer (PC). For example, they may be used in such applications as video conferencing, document capturing, pattern recognition, process quality control, and games. Desired characteristics for these cameras include a small form factor, low power consumption and fast capture rates. Another important feature of these cameras will be the possibility of programming the resolution of either the whole image or a part of the image.
The analog to digital (A/D) converter is an strategic component in any digital camera as it often consumes a substantial part of the total power budget, occupies a large area and is a bottle neck for speed. However, if the A/D converter is properly designed, resolution programmability and many focal plane processing steps (e.g., image processing that are performed on the image sensor) may be made at conversion time.
In conventional cameras using complementary metal oxide semiconductor (CMOS) sensor arrays and integrated A/D converters, each column of pixels in the CMOS sensors has an A/D converter. When A/D converters are integrated in the same chip as the sensors, usually single slope converters are used for their simplicity and compaction. However, the size of the comparator portion of the converter circuit will not scale as well as the sensor array and other digital parts. Moreover, the power consumption of the A/D converter array is usually very high. It is also not easy to program these A/D converters for different resolutions.
One solution to the problems mentioned above is to replace the A/D array by a few or a single A/D converter. However, the resulting performance of the A/D converter of this approach, assuming a 1,000 pixel high by 1,000 pixel wide sensor array and a frame rate of 30 frames per second (fps), must be able to accommodate captures of 30 million samples per second with resolutions of up to 10 bits per sample. These requirements may be met by a single pipeline, parallel, or flash converter. But, the power consumption of these converters, although less than an A/D converter array, are still high. In addition, frame rates higher than 30 fps, even if possible, are very difficult to achieve with these converters. Thus, it is desirable to have an A/D converter which overcomes one or more of the deficiencies noted above.